Hello Memory Enthusiasts! Please see here a guest post by the distinguished Patrick Moran Thanks Pat for allowing the repost!
LPDDR4 was introduced in 2014 about two years after LPDDR3. This was probably the fastest transition for a new generation memory ever in JEDEC history. New products and features being introduced into the mobile ecosystem requiring faster and lower power memory propelled the fast development. LPDDR4 succeeded in increasing maximum data rates from 1866 Mbps to 3200 Mbps. But active power results for initial products were disappointing since operating voltage was reduced by only 7%.
The industry responded with LPDDR4X early in 2017. The ‘X’ stands for ‘eXtra’ or ‘eXtended’. It headlined lower I/O voltage to save system power and new features to kick the data rate from 3200 to 4266 Mbps. Today it has replaced the original LPDDR4 for new designs (LPDDR4 remains available for legacy systems.)
Think of LPDDR4X as LPDDR4 done right.
What makes a good LP DRAM and where did LPDDR4 come up short?
Two things really - active power and standby power.
Maximum active power occurs when the mobile device is operating at full speed, for example playing an action game, and includes memory device power and the power the system uses to operate the memory. An aggressive goal for a new generation of LP DRAM might be the same power at its full speed for the new generation LP DRAM. For example, a LPDDR4 at its max speed of 3200 Mbps might consume the same power as a LPDDR3 operating at its max speed of 1600 Mbps. The least aggressive goal would be that active power remains the same at a given speed (e.g. LPDDR3 and LPDDR4 consuming the same power at 1600 Mbps with LPDDR4 power increasing above 1600 Mbps).
Standby power broadly refers to power consumed by the device when it is waiting for the user to awaken it. A reasonable goal is for the new generation device to consume less power than its predecessor using an apples-to-apples technology comparison. For example, an 8Gb LPDDR3 memory built with 2y nm technology compared to an 8Gb LPDDR4 memory built on the same tech node.
Improvements can from either reducing memory voltages or inventing new operating modes that use less power.
LPDDR4’s 7% operating voltage reduction compared to LPDDR3 (1.2 to 1.12 V) achieved some standby power reduction. However, even with the introduction of new features like DBI, this reduction was not enough to reduce I/O power at the higher LPDDR4 speeds. A more refined approach on both the memory and system sides was needed. Enter LPDDR4X.
LPDDR4X – What’s new?
The biggest change is the reduction in I/O voltage (VDDQ) by almost 50% (1.12 to 0.61 V) creating an obvious power reduction on both the memory and system sides of the bus. This savings turned out to be compelling for applications even considering the added cost to generate a new voltage I/O power supply in the system.
Maximum data rate was increased from 3200 to 4266 Mbps by adding termination and calibration options. Newer system PHY’s were designed to leverage these options and provide more deskewing on the system side. Systems also started to make more use of periodic calibration functions introduced in LPDDR4.
Unfortunately, LPDDR4X is not backward compatible to LPDDR4. LPDDR4X devices are not required to be compatible with or tolerate higher LPDDR4 voltage on their I/O. Also, there is no specified way to query a LPDDR4 or LPDDR4X device to determine its type during the power-up sequence. This is not as bad as it sounds since LPDDR memory devices are not user (or even technician) replaceable once installed by the manufacturer.
Sorting out the JEDEC specs
JEDEC has published two LPDDR4 specifications which are available for download describing LPDDR4. The base specification is JESD209-4 (currently at Revision B). It contains information for both LPDDR4 and LPDDR4X. The other is JESD209-4-1 which is described as an addendum. The addendum is intended to describe differences / additions / deletions applicable to LPDDR4X compared to the base LPDDR4 spec.
In practice, users should carefully compare the two specifications to determine functionality deltas. For example, Mode Register 0 is shown in its entirety in both specs. But a detailed comparison shows that the real difference is that the OP[7] bit (CATR) exists in LPDDR4, but is reserved in LPDDR4X.
Readers: If you have LPDDR4 or LPDDR4X designs that need analysis think FuturePlus! We have BGA Interposers, equipment and services to assist in your validation and testing.
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