The Threat That Just Keeps Getting Bigger: DRAM Row Hammer
Row Hammer. The problem no DRAM vendor wants to talk about, except for one, Zentel
Provided Courtesy of Zentel
LPDDR5 vs LPDDR4: What’s the difference?
Recently JEDEC announced the new JESD209-5 Low Power Double Data Rate 5 (LPDDR5) specification. LPDDR5 is faster and lower power than its predecessors LPDDR4 and LPDDR4x. Want a copy of the specification? Click Here
LPDDR4 to LPDDR4X: What is the difference?
Hello Memory Enthusiasts! Please see here a guest post by the distinguished Patrick Moran Thanks Pat for allowing the repost!
What is DDR4 Memory Gear-Down Mode?
A Reliability, Availability and Serviceability (aka RAS) feature more clearly documented in the new JEDEC DDR4 Rev B spec, Gear-down mode, allows the DRAM Address/Command and Control bus to use every other rising clock of the DDR4 Memory bus clock.
Is your DDR4 Memory Controller Compliant?
Finally! After 2 ½ years FuturePlus Systems was successful in sponsoring JEDEC’s first document on protocol checks, JEP175 DDR4 Protocol Checks. But we didn’t do it alone! Many thanks to the other Test and Measurement vendors, EDA vendors and ...