FAST SODIMMS for DDR4 are here!
Traditionally SODIMMs (Small Outline DIMM) have been used in the mobile environment because of their smaller size. For DDR3 SODIMMs did not have ECC so they were not even considered for Servers. When DDR4 was created there was discussions within JEDEC for SODIMMs to be used in more robust environments so ECC was added to the specification. However, due to the smaller mechanical size of an SODIMM, memory capacity is limited. Here at FuturePlus we make sure all our DDR Validation Tools work in a variety of systems and at all supported speeds. The best way to do that is to validate our tools in as many platforms as we can get our hands on. Which leads me to this little baby!
So how does this memory bus look?
Take a look at those EYES! This is a burst scan of both the read data and write data. You can see that the eyes allow for ample margin for signal capture. This Asrock system looks, well….rock solid!
Above is a screen shot of the Address/Command/Control bus. You can see that the bus is 2T timing, meaning that the Address/Command/Control signals are held for two cycles instead of one. However, the Chip Select signal was only held for one cycle. Had it been doubled the Memory Controller would have had to operate in Gear Down mode. Interesting to note, we have never seen an Intel based platform operate in Gear Down Mode.
Most folks don’t think that a logic analyzer can be used for analog analysis but it can! As you can see a SODIMM slot interposer with a logic analyzer allows us to quickly find which bits are bad and then, if need be, we can use our high bandwidth scope on the signals that don’t look quite right. This qualitative comparative analysis lets us see all of the DDR bus signals at the same time. Something you cannot do with a scope.
Got a problem with your system? Let us help. You too can be the owner of the equipment that performed these fine measurements! OR you can have us make the measurement for you. We also offer services.