FuturePlus Systems

Find root cause of Memory failures don't just throw the DIMM away!

Many medical device manufacturers are experts on the medical portion of their product, but what about the compute engine? This is the part that does not touch the patient but makes the decision based on the data. Many medical device manufacturers ...

Those of you who read my previous Blog post on the new DDR4 Revision B spec know that DDR4 has a much better defined Rounding Algorithm. So why is this important?

Finally! After 2 ½ years FuturePlus Systems was successful in sponsoring JEDEC’s first document on protocol checks, JEP175 DDR4 Protocol Checks. But we didn’t do it alone! Many thanks to the other Test and Measurement vendors, EDA vendors and ...

The JEDEC JC42.3 committees have issued the B version of the DDR4 specification. This version is several years in the making as the original JESD 79-4 DDR4 SDRAM specification was released in September 2012 and the A version published in November of ...

JEDEC’s DDR5 Announcement certainly came as no surprise to those of us working on the standard behind the scenes. The new 5th generation memory bus will have two, 32 bit channels complete with its own Address/Command and Control signals. ECC and CRC ...

Page Hit and Miss is often a metric used to describe caching architectures. In this context a Hit is when the page was already open and the Read/Write transaction occurred. A Miss is when an Activate[1] had to occur just prior in order to open the ...

For DDR4 there are 11 different modes and these metrics are Rank based. These include the following: Reset, Idle, Active, Precharge Power Down, Active Power Down, Maximum Power Down Mode, Self-Refresh, DLL Disable, Write Leveling, MPR Mode (also ...

If you are Facebook and its 3 am on the East Coast of the United States you probably want to see your Servers in a low power state. This can save you money and make your server farms more ‘green’.

There are two types of latency to consider when looking at the cycle by cycle transmission of data on the DDR4 Data Bus. The first is the time between the Read or Write command and the data associated with that command, refered to as CAS and CAS ...